A flash-type analog-to-digital converter circuit (referred to as an “A/D converter circuit”) includes a plurality of comparators (voltage comparators) that receive an analog input signal in parallel, a reference circuit for supplying the plurality of comparators with respective ones of reference voltages having levels that differ from one another, and an encoder for receiving the results of the comparison operations that are output from the plurality of comparators, encoding these signals and producing a digital output signal (see FIG. 1). Flash A/D converter circuits are used generally for high-speed applications and require a track-and-hold circuit (TH circuit) (10 in FIG. 1) for sampling of the input analog signal. A/D converter circuits having an on-chip TH circuit also are available on the market. As shown in FIG. 2, a TH circuit typically is equipped with a switch 101, a capacitor 102 and a buffer 103. When the switch 101 is closed, an input analog signal from an input terminal (IN) is sampled. When the switch 101 is opened, a voltage (the terminal voltage of the capacitor 102), which has accumulated in the capacitor 102, is output from the buffer output (OUT).
The reference circuit (20 in FIG. 1) generates n (where n is 2m, and m is a prescribed integer) reference voltages and supplies these to reference-voltage (reference-voltage) input terminals of respective ones of n comparators. As shown for example in FIG. 8, the reference circuit typically includes a voltage-dividing resistor circuit comprising resistors R1 to Rn connected in series between a reference top potential (VRT, which is the highest potential among the reference voltages) and a reference bottom potential (VRB, which is the lowest potential among the reference voltages). The top and bottom potentials VRT and VRB, respectively, and the reference voltages between them are extracted from taps (the connection terminals of the resistors R1 to Rn) and are supplied to the corresponding comparators.
By way of example, Patent Document 1 discloses a variable reference level generating circuit of a flash-type A/D converter circuit. In the disclosed A/D converter circuit, an input signal is supplied to a plurality of comparators provided in parallel, the comparators are supplied with respective ones of reference voltages the levels of which differ from one another, and the outputs of the comparators are encoded. The input signal is supplied via a sample-and-hold circuit, and a circuit that forms the reference voltages also is provided with sample-and-hold circuits having characteristics identical with those of the circuit to which the input signal is applied. This arrangement is such that sample-and-hold circuits (the sample-and-hold operation of which is controlled by the sampling pulses) are connected to respective ones of a reference top potential supply terminal and reference bottom potential supply terminal, a voltage-dividing resistor circuit is provided between outputs of these two sample-and-hold circuits and the reference voltages are supplied to corresponding comparators from the taps of the resistor circuit. The voltage-dividing resistor circuit is constructed as shown in FIG. 8. In this specification, the track-and-hold circuit (TH circuit) that samples and holds the input signal is essentially synonymous with a sample-and-hold circuit (SH circuit) that samples and holds an input signal.
Non-Patent Reference 1 discloses an arrangement in which a reference circuit (reference voltage generator) that generates reference voltages for a comparator array applies a common-mode reference voltage Vcmi to a sample-and-hold circuit (SHREF) comprising a replica circuit of a main sample-and-hold circuit (main S/H circuit), and a reference top potential Vrefp {=Vcmr+[(Iref)(R2)/2], where Iref represents a reference current that has been generated from a band-gap reference voltage} applied to one end of a voltage-dividing resistor circuit is generated by an amplifier (A2), which receives an output Vcmr of the sample-and-hold circuit (SHREF) at a non-inverting input terminal, and a feedback resistor (R2, this being connected between an inverting input terminal and output terminal of the amplifier A2). A constant-current source is connected to one end of the voltage-dividing resistor circuit in the reference circuit of Non-Patent Reference 1.
Further, Patent Reference 2 discloses an arrangement in which a voltage-dividing resistor circuit is constructed by providing a transistor forming a first variable resistor, a fixed resistor and a transistor forming a second variable resistor between a power-supply potential VDD and ground potential GND. Nodes of the variable resistors and fixed resistor are connected to first and second voltage followers, the output voltages of the first and second voltage followers are sent to an A/D converter as reference voltages, and reference voltages are supplied to comparators from the taps of a resistor array (voltage-dividing resistor circuit) connected across the output voltages of the first and second voltage followers.
[Patent Document 1]
Japanese Utility Model Kokai Publication No. 63-31625 (FIG. 1)
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-9-116435 (FIG. 1)
[Non-Patent Document 1]
Krishnaswamy Nagaraj, David A Martin, Mark Wolf, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, and T. R. Viswanathan, “A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25-μm Digital CMOS Process,” IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 35, NO. 12, pp. 1760 to 1768, DECEMBER 2000, (FIG. 15)
A buffer circuit used in a track-and-hold circuit of a high-speed A/D converter circuit requires a wide band, and hence there are such cases where it is difficult to achieve a desired high gain in terms of a given GB (Gain Bandwidth) product. For this reason, gain error tends to occur in a track-and-hold circuit that includes a buffer circuit.
Further, an offset error is produced in a case where a source follower is used in a buffer circuit employed in a track-and-hold circuit.
Gain error and offset error in a buffer circuit that supplies an input signal to a comparator cause gain error and the like in an A/D converter circuit. These errors vary depending upon the process, power-supply voltage and temperature, etc. This in turn leads to a variance in conversion precision and degradation of DC, AC (dynamic) characteristics or the like.